Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/02/2013 08:46 AM, Per Karlsson wrote:

> Apart from floorplanning a hierarchical netlist is necessary for
> benchmarking (area, power, routing, timing...). It is nigh impossible
> to figure out what's going on in your design with a flat netlist.

I have nowhere questioned the potential usefulness of hierarchy -
merely the usefulness of floorplanning. I would like to
hear the opinion of other FPGA experts on this.
Ideally based on experiments.

I use hierarchy in the output regularly, often for clarity. I
use user-defined code for this and I think it works quite well.

Simply convert at various levels, and use user-defined code
(under parameter control) for instantations.

> Finally, worrying about target dependence is missing the mark.
>
> Every design is target dependent. You can try your best to fit a
> range of targets, but there is always a dependence.

You go over it very lightly it seems. Of course there will be
unavoidable dependencies. But "opening the gates" because of
this observation is very unwise.

I have seen many cases of vendor lock-in with a very high
economical cost that could perfectly have been avoided.
Conversely, my own experience has been to use HDL design
to keep dependencies minimal - with considerable success.

What I am questioning here is not the concept of hierarchical
output, but the proposed solution which seems to suggest
signifant, non-parametrizable, non-functional source code
changes to infer it. I don't like that.

Note there are 2 alternative solutions today. One which
works with current MyHDL, based on user-defined code.
Another is Oscars' proposal which I have not reviewed yet,
but which I believe requires no source code changes at all.
Both these solutions could probably be improved, but
I think they are conceptually much better.

Jan

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