Re: [myhdl-list] 0.8.1 bug fix release scheduled

[Christopher F. <chr...@gm...>]

<snip>
> Consequently, I plan a bug fix release 0.8.1 soon. If
> there are any other *critical* bugs, we can address
> them also - but no new features or major changes.
>

There is a bug (I believe) in the tri-state
conversion for Verilog, it appears to work in
VHDL.  It has been awhile since I looked at this,
I believe the issue is simply the port definition
is not /inout/ in the Verilog conversion.

I can write a test for this but it will probably
be a week before I can get to it.  Example code
here.

https://gist.github.com/cfelton/6119313

Regards,
Chris