Re: [myhdl-list] attribute enum_encoding: string;

[Jan D. <ja...@ja...>]

Mm, this fails on toVHDL() already, regardless of the
encoding ... something else is wrong here.


On 09/12/2013 08:19 AM, David Holl wrote:
> On Tue, Sep 10, 2013 at 12:28:25PM +0200, Jan Decaluwe wrote:
>> Mm, I suspect there will still be a bug iff an
>> enum type is used at the top-level.
>>
>> If someone provides a failing test case, I'll
>> fix it :-)
>
> Wish granted.  :)  I've attached a test that fails on MyHDL 0.8.  Pardon the
> contrived example; I lobotomized a perfectly functioning state machine to
> achieve using a top-level enum.  (reduced to 2 states, removed PCIe junk...)
>
> It passes toVerilog and conversion.analyze (with .simulator='icarus').
>
> But it will fail during toVHDL, or if you comment out the toVHDL test, it will
> also fail during conversion.analyze (.simulator='GHDL') with this error:
>
>
> subspace(ttys003):~> python test_enum_toVHDL.py
> Analysis succeeded  <-- This message is after passing toVerilog & icarus
> Traceback (most recent call last):
>    File "test_enum_toVHDL.py", line 48, in <module>
>      toVHDL(pcie_legacyint_next_state_logic, state, next_state, next_state_en, interrupt_pending, interrupt_assert)
>    File "/Users/dholl/Library/Python/2.7/lib/python/site-packages/myhdl/conversion/_toVHDL.py", line 173, in __call__
>      assert obj in _enumTypeSet
> AssertionError  <-- This is upon trying either toVHDL or ghdl analysis.
>
>
> - David
>
>
>>
>> On 09/09/2013 02:43 PM, David Holl wrote:
>>> ugh!  My asinine filesystem lockdowns had prevented any recent updates to myhdl, and I had been stuck on an old 0.8dev from Nov 9, 2012.  Updating to the latest 0.8 fixed the problem.
>>>
>>> The vhdl output from the Nov 9th 0.8dev did indeed have a top-level package declared before any other statements such as "use work.pck_myhdl_08.all;"
>>>
>>>      package pck_pcie_drx is
>>>           type t_enum_t_state_1 is (
>>>           SM_RESET,
>>>      ...
>>>
>>> (but my design does not use any enum's in the ports)
>>>
>>> However in the vhdl from the latest 0.8, there is no top-level package, and the code opens with
>>>
>>>      library IEEE;
>>>      use IEEE.std_logic_1164.all;
>>>      use IEEE.numeric_std.all;
>>>      use std.textio.all;
>>>      use work.pck_myhdl_08.all;
>>>      entity pcie_drx is
>>>           port (
>>>               user_clk: in std_logic;
>>>      ...
>>>
>>>
>>> Thank you Chris and Jan for looking into this!
>>> - David
>>>
>>>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
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