Re: [myhdl-list] MyHDL : The Case for a Better HDL

[Christopher F. <chr...@gm...>]

On 8/26/2013 5:04 PM, Jonas wrote:
> Christopher Felton <chris.felton <at> gmail.com> writes:
>
>> For more information on the first topic, see Jan's "These Ints are Made
>> For Countin'" essay http://jandecaluwe.com/hdldesign/counting.html.
>
>> For me, the "RTL abstraction" section touched on some important points.
>>    How do you effectively teach complex digital systems architecture and
>> implementation (HDL) and the low-level digital circuits?  I see this as
>> a failure in the current education sytle.  We teach the digital systems
>> and HDL the same as the digital circuits, from the bottom-up.  Even
>> folks that are teaching themselves HDL appear to fall into folly.
>
> I was working with VHDL a while ago. I liked a lot the very flexible type
> system and the philosophy about code readability even if it results in more
> typing. All those good features comes from Ada, on which VHDL was greatly
> inspired. From all the languages I know, I see Ada as the best source of
> inpiration for an HDL, because you could have a very flexible language with
> high level constructs (for each loops, array slicing, attributes, ...), but
> with the possibility of specifying low level details.

I believe Jan D. has similar views, see the Ada
reference in the /modbv/ MEP:
http://myhdl.org/doku.php/meps:mep-106

<snip>
>
> A bigger reason of my bad experience with VHDL, was the persistant mentality
> among the community of VHDL to think low level only, even in situation when
> thinking high level makes a lot more sense.

Amen, your preaching to the choir!  Emphasis on
the *only*.  Need to navigate the trees and the
forest.

>That leaded to absurd and
> outdated coding standards like transforming everything to std_logic or
> std_logic_vector in the ports of entities (including unsigned/signed signals
> although they are represented exactly the same way as std_logic_vector)
> instead of keeping the higher level types, which makes it harder to read and
> more error prone. And those coding standards gets imposed upon you but
> nobody can tell you why. All you hear is something like "the VHDL experts
> told that it has to be done that way".
>

The infamous "experts" :)

> Even if it sounds weird to me to use python to do HDL, at least I like the
> idea of bringing modern ideas and a different mentality in the HDL community.
>

One thing you probably (I stand on limbs) don't find
absurd, is the use of a high-level language for modeling
and verification.  The use of Python for digital system
modeling and verification is very nice, very nice.  And
it is a bonus

Regards,
Chris