Re: [myhdl-list] MyHDL : The Case for a Better HDL

[Jonas <jon...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:

> For more information on the first topic, see Jan's "These Ints are Made 
> For Countin'" essay http://jandecaluwe.com/hdldesign/counting.html.

> For me, the "RTL abstraction" section touched on some important points. 
>   How do you effectively teach complex digital systems architecture and 
> implementation (HDL) and the low-level digital circuits?  I see this as 
> a failure in the current education sytle.  We teach the digital systems 
> and HDL the same as the digital circuits, from the bottom-up.  Even 
> folks that are teaching themselves HDL appear to fall into folly.

I was working with VHDL a while ago. I liked a lot the very flexible type
system and the philosophy about code readability even if it results in more
typing. All those good features comes from Ada, on which VHDL was greatly
inspired. From all the languages I know, I see Ada as the best source of
inpiration for an HDL, because you could have a very flexible language with
high level constructs (for each loops, array slicing, attributes, ...), but
with the possibility of specifying low level details. Unfortunately VHDL
wasn't as much fun as it could be for several reasons. One reason was that
VHDL use the good concepts from Ada only halfway. For example the numbers
management. numbers (signed and unsigned) where defined as array of
characters, so they were represented like strings. Then working with them,
doing mixed arithmetics with integer and signed or unsigned wasn't that
natural and has some quirks. In Ada you can optionnally tell the hardware
representation of a variable or a type with a "for ... use" clause. Why not
using such a mechanism in VHDL and than use signed and unsigned types as
real integer ? Then working with numbers could be as easy as that :

  -- VHDL builtins
  type unsigned is range 0 to ∞;
  subtype sys_unsigned is unsigned range 0 to MAX_UNSIGNED;
  --

  variable A : sys_unsigned;
  variable B : unsigned slice 7 downto 0;
  variable C : unsigned slice 8 downto 0;

  A := 2;
  B := A.Fit; -- Resizing is needed here
  C := B + B;
  -- Repr attribute give the hardware representation
  B'Repr <= A'Repr(5 downto 0) & "00"; 

We can even extend the mecanism to other things like enumerate types :

  type Enum is (A, B, C) with (A => "00", B => "11", C => "01");
  type Enum_2 is (D, E, F, G) with Gray_Encoding;

A bigger reason of my bad experience with VHDL, was the persistant mentality
among the community of VHDL to think low level only, even in situation when
thinking high level makes a lot more sense. That leaded to absurd and
outdated coding standards like transforming everything to std_logic or
std_logic_vector in the ports of entities (including unsigned/signed signals
although they are represented exactly the same way as std_logic_vector)
instead of keeping the higher level types, which makes it harder to read and
more error prone. And those coding standards gets imposed upon you but
nobody can tell you why. All you hear is something like "the VHDL experts
told that it has to be done that way".

Even if it sounds weird to me to use python to do HDL, at least I like the
idea of bringing modern ideas and a different mentality in the HDL community.