Re: [myhdl-list] MyHDL Tristate Logic

[Jan C. <jen...@mu...>]

On 09/08/13 23:48, Alexander Hungenberg wrote:
> Thank you for your replies.
> I did now indeed switch to the manual way Jan described. Didn't 
> know that this was possible before. :-)
>
> With this I managed to advance quite a bit with my I2C module but 
> just ran into a new problem. When converting the module to VHDL / 
> Verilog I get a warning
> "** ToVHDLWarning: Output port is read internally: sda_oe" 
> (sda_oe is the output enable signal)
> So far so good, but I nowhere do access the value of sda_oe 
> internally.
Converting just I2CByte generates the error:  "Output port is read 
internally: scl"  Using a separate signal for the output fixes 
this, as per regular VHDL code.  Showing changes in part of your 
code, which must also add the new signal:

     # we will update SCL at clock negedges so that we may alter 
SDA on the posedges
     @always_seq(clock.negedge, reset=reset)
     def scl_driver():
         if state == STATES.IDLE:
             scl_i.next = False
         elif state == STATES.START:
             scl_i.next = False
         elif state == STATES.TRANSMIT:
             scl_i.next = not scl_i
         elif state == STATES.STOP:
             scl_i.next = False

     @always_comb
     def port_out():
       ''' write output ports '''
       scl.next = scl_i

     return single_byte, scl_driver, port_out

There is the same problem in I2CBurstProtocol.

Hope this helps, Jan Coombs.
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