[myhdl-list] MyHDL Tristate Logic

[Alexander H. <ale...@gm...>]

Hi all!

I'm a new user of this very nice piece of software but unfortunately
stumbled upon some problem while implementing tri-state logic (of course
for an I2C module). Originally I wrote directly to Jan (thank you for your
reply!) and he pointed me to this mailing list.

Regarding my problem, I am not sure whether it is a bug in MyHDL or my
fault, but the generated Verilog code looks wrong to me.

MyHDL: http://pastebin.com/sQRnRPFL
Verilog: http://pastebin.com/qVzew9wg

Especially the fact that tristate is declared as output and not inout as
well as the three assign lines make me kind of nervous. Do you have any
idea?

Best,
Alex