[myhdl-list] Question about conversion of slice types

[Martin S. <ha...@se...>]

Hi list,

for a few reasons, one of them being switchable external definitions,
I'd like to define slice types as follows:

OP_INDEX = slice(11, 8)
OP_MODE = slice(8, 6)

and use them later in the HDL. No problem in the native simulation, but
obviously, myhdl would not convert the slice type into VHDL. I've done
some patching in the AST-featured visitors to turn the slice into a subtype:

    subtype OP_INDEX is integer range 11-1 downto 8;

to be used by the HDL conversion as:

        index := resize(opcode(OP_INDEX), 11);

Now with the new shadow signals, in particular the slice signal, a
presumably much more elegant solution is possible, but when I tried
last, it wouldn't infer the signal for some reason (not investigated
further). I'm using the 0.8 sourceforge distribution.

Apology if I'm bringing up some FAQ, but does anyone see reasons not to
do it this way or problems for the Verilog conversion side?

Cheers,

- Strubi