Re: [myhdl-list] Summary of "Initial Values Support" threads

[Norbo <Nor...@gm...>]

Am 27.06.2012, 06:26 Uhr, schrieb Christopher Felton  
<chr...@gm...>:

> On 6/15/12 4:12 AM, Jan Decaluwe wrote:
>> On 05/30/2012 06:47 AM, Christopher Felton wrote:
>>> We listed a summary a couple time but the initial value support (ivs)
>>> was embedded in a separate thread.  So, I thought it would be worth
>>> while to summarize in a new thread.
>>>
>>>
>>>      1.  Initial value support can be re-enabled.  The Verilog
>>>          support of initial values as verified with the latest
>>>          of Quartus.
>>>          Need to test with (list syn and sim tools)?
>>>            [x] Quartus latest
>>>            [ ] ISE (xst) latest
>>>            [ ] cver
>>>            [ ] icarus
>>
>> Ok, perhaps make a page on the site to keep track
>> of the status.
>>
>
> I created a wiki page and essentially copied the latest summary to the
> wiki page, it is a little rough right now.
>
> http://www.myhdl.org/doku.php/dev:initial_values
>
> Regards,
> Chris


I am now sure that the lattice diamond Synthesis Tool v2.1 works with  
memory initialisation infered from the code.
You may ask why?
Answer: The Initialisation of the memory didn't worked when the bitwidth  
of the memory exceeded 9 Bits. Everything that was above 9 bit was  
initialized to "0" on the fpga. The synthesis tool showed no error.
I had a long chat with the technical support. And know in v2.1 of the  
Latic Diamond Synthesis Tool they fixed this Glitch.
At the core they use Synplify pro for synthesis. But i think it was a  
mapping problem in there tool.

Hope that helps brings forward initial value support in Myhdl one Day.

Greetings
Norbo