Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

>This is a typical difficulty: with limited RTL experience it
>is often difficult to make the distinction between limitations
>imposed by synthesis, and MyHDL itself.

This is true, I ended up doing proof of concept work in verilog and
migrated to myhdl to use python for algorithmic data generation. MyHDL
certainly facilitates fine grained control for distributing data across
memories.


>I'm sure people will be interested in reviewing your code and
>giving feedback.
It is a funded project, so I will have to look into the terms. I will try
to share the code with the community ASAP!

>But there's the point already. Those arbitrary data structures are
>not there as such in Verilog/VHDL. So there is the nontrivial difficulty
>on how to map them into those target languages, and how generic
>this should be.
It is implied that references to these data structures should point to
MyHDL primitives.
For example, MemorySubsystem['a'].tag_memory[2].dout, which is a MyHDL
Signal object. (Overly complex example to show the possibilities). I will
search the mailing list and codify my ideas sometime next month.





On Wed, May 15, 2013 at 3:35 PM, Jan Decaluwe <ja...@ja...> wrote:

> On 05/15/2013 09:08 PM, Keerthan jai.c wrote:
>
> >> To remove doubts, you could perhaps tell a little more about
> >> yourself, your experience, past projects, etc.
>
> > I'm a computer engineering graduate student and my academic focus is
> > on computer architectures and acclerating algorithms using FPGAs. I
> > am an inexperienced RTL Developer. Currently my past projects and
> > experience in RTL are limited to minor academic and personal
> > projects.
>
> This is a typical difficulty: with limited RTL experience it
> is often difficult to make the distinction between limitations
> imposed by synthesis, and MyHDL itself.
>
> Unfortunately, the reason is that RTL is not very well documented
> for beginners. Also unfortunately, it implies that MyHDL is not
> necessarily a good way for beginners to learn HDL design.
> I wish it were different, but that's the way it is.
>
> >  However, I will be open-sourcing a slightly complex
> > application early next month(A lot of it is written with MyHDL!). I'm
> > currently in the process of cleaning up its code before documenting
> > it and packaging it.
>
> Excellent. You are an active user. We're listening.
>
> I'm sure people will be interested in reviewing your code and
> giving feedback.
>
> >> Secondly, the convertor is not a synthesis tool - it maintains the
> >> abstraction level. Therefore, there has to be some way to map
> >> supported MyHDL code to Verilog/VHDL in a reasonably direct way.
> >> Hence the supported primitives are defined by those that exist in
> >> the target languages.
>
> > I understand this. I do not mean that the converter should work with
> > arbitrary python code. It should however be able to handle arbitrary
> > data structures (MEP 107).
>
> But there's the point already. Those arbitrary data structures are
> not there as such in Verilog/VHDL. So there is the nontrivial difficulty
> on how to map them into those target languages, and how generic
> this should be.
>
> As for your investigation, it may be a good idea to start by
> reviewing all the past communications on the issue.
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
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-- 
have a nice day
-jck