Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

On 5/15/2013 9:10 AM, Keerthan jai.c wrote:
> I did mention in the first post, that I've benifitted from MyHDL for
> testing. I was merely curious about how other users cope with the
> restrictions of conversion.
>
> On another note, do you think that using AST is the best approach for
> conversion? I think, in a language like python, where everything is an
> object, looking only at variable names feels a bit fragile.
>

This might help understand the MyHDL goals (or not)
from my perspective.  MyHDL is intended to be an HDL
and not a Verilog/VHDL code generator.

These three pages should give a good overview for the
project and philosophies:

    http://myhdl.org/doku.php/overview
    http://myhdl.org/doku.php/why
    http://myhdl.org/doku.php/whatitisnot

The MyHDL language design is important and should not
be under appreciated.  Look at the effort and thought
that went into the underlying Python language design.
Since, MyHDL lives in Python it has similar goals and
philosophies.  Jan has done a good job considering the
language design for an RTL level HDL.

 From this context it makes absolute sense to use the
Python front-end parsing tools and the AST representation,
otherwise you can end up with a very ugly HDL or spend
significant time re-implementing the same tools.  As Jan
mentioned more than simply the /name/ is available from the
AST tools, you have access to the objects.

This is from my perspective, Jan or others can correct
or chime in where necessary.

Regards,
Chris