Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

I did mention in the first post, that I've benifitted from MyHDL for
testing. I was merely curious about how other users cope with the
restrictions of conversion.

On another note, do you think that using AST is the best approach for
conversion? I think, in a language like python, where everything is an
object, looking only at variable names feels a bit fragile.



On Wed, May 15, 2013 at 8:10 AM, Jan Decaluwe <ja...@ja...> wrote:

> On 05/13/2013 10:01 PM, Keerthan jai.c wrote:
> > Thanks, I will look at your examples.
> >
> > What about the two logic blocks mem_a and mem_b? They are essentially
> > the same logic, the only difference being their ports. Is there
> > anyway to make that more elegant? Is reducing the repetition of
> > information a part of myhdl's vision?
>
> The fact that you ask a rethorical question like this
> suggests that you don't completely grasp what MyHDL is
> about.
>
> It is not only about conversion and implementation, but
> also (perhaps even more so) about modeling and test benches.
>
> The modeling/test benches part is intended to be very generic.
> You should be able to use most Python features in the book
> to do it as you want.
>
> It's the conversion part that has the restrictions. This has
> all kinds of reasons, e.g. restrictions in Verilog/VHDL and
> the mere fact that such a conversion from a dynamic to
> static languages is not trivial.
>
> Please do make that distinction between modeling versus restrictions
> related to conversion.
>
> I understand that people expect all kinds of additional features
> from conversion. But you know - I think it's quite powerful
> as it is, *if you compare it with restrictions imposed by
> VHDL/Verilog synthesis itself*. Note that the main reason for
> conversion still is a path to synthesis.
>
> I don't see the occasional workaround as a problem. Moreover,
> as conversion is here and there already to tricky to my taste,
> I'm not looking for all kinds of new features except when they
> have an obvious significant additional value. I'd rather
> incorporate "boring" and "invisible" improvements that
> increase robustness.
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
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-- 
have a nice day
-jck