Re: [myhdl-list] Proposal: New class, ClockDomain
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From: Jan D. <ja...@ja...> - 2013-05-15 07:11:59
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On 05/15/2013 02:22 AM, Keerthan jai.c wrote: > Do you think it is a good idea to have a new class ClockDoman, Not in the myhdl library itself, and not enough value to support for conversion. which contains a clock and reset signal? Typically, we use the same clock and reset signals for most modules, having a clock domain object might simplify this. > > Example: > def module(cd, ports...): > @always_seq(cd) > .... > > clk = Signal(bool(0)) > rst = ResetSignal(1, active=0, async=True) > app_clk = ClockDomain(clk, rst) > > inst = module(app_clk, ports.. > > > -- > have a nice day > -jck > > > ------------------------------------------------------------------------------ > AlienVault Unified Security Management (USM) platform delivers complete > security visibility with the essential security capabilities. Easily and > efficiently configure, manage, and operate all of your security controls > from a single console and one unified framework. Download a free trial. > http://p.sf.net/sfu/alienvault_d2d > > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |