Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

On 5/13/2013 3:54 PM, Keerthan jai.c wrote:
> I suppose I could have done this:
>
> def mem_logic(clk, data, addr, we, q, mem):
>      @always(clk.posedge)
>      def logic():
>          if we:
>              mem[int(addr)].next = data
>          else:
>              q.next = mem[int(addr)]
>      return logic
>
>
> def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
>                  we_a, we_b, q_a, q_b, depth=128):
>      """Ram model"""
>
>      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>
>      mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>      mem_b = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
>
>      return mem_a, mem_b
>
>

Also valid:

     ...
     mem = [Signal(intbv(0)[8:]) for i in range(depth)]
     mem_ports = [None,None]
     mem_ports[0] = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
     mem_ports[1] = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)

     return mem_ports

In addition, I am fairly sure, in this case you could do
(would need to test first):

     def DPR(clk pa, pb):
         mem = [Signal(intbv(0)[8:]) for i in range(depth)]
         mem_ports = [None,None]
         for inst,port in zip((mem_ports,(pa,pb)):
             inst = mem_logic(clk, port.data, port.addr,
                              port.we, port.q, mem
         return mem_port

NOTE! I did not test the above, I did not even
check the syntax.

Regards,
Chris