Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Norbo <Nor...@gm...>]

 From a RTL point of view the following code has the same functionallity.
But be aware some synthesis tools need this specific way of writting the  
vhdl/verilog code inorder to
succesfully infere a dual ported ram. But i think most of the newer tools  
will recognize.


def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
                 we_a, we_b, q_a, q_b, depth=128):
     """Ram model"""

     mem = [Signal(intbv(0)[8:]) for i in range(depth)]

     @always(clk.posedge)
     def mem_both():
         if we_b:
             mem[int(addr_b)].next = data_b
         else:
             q_b.next = mem[int(addr_b)]

	if we_a:
             mem[int(addr_a)].next = data_a
         else:
             q_a.next = mem[int(addr_a)]

     return mem_both


best greets
Norbo


> Thanks, I will look at your examples.
>
> What about the two logic blocks mem_a and mem_b? They are essentially the
> same logic, the only difference being their ports. Is there anyway to  
> make
> that more elegant?
> Is reducing the repetition of information a part of myhdl's vision?
>
>
> On Mon, May 13, 2013 at 3:52 PM, Christopher Felton
> <chr...@gm...>wrote:
>
>> On 5/13/2013 2:15 PM, Keerthan jai.c wrote:
>> > Hi,
>> >
>> > I have been using myhdl for some time now, and while writing tests  
>> using
>> > myhdl are clearly simpler and more powerful than using verilog/vhdl, I
>> feel
>> > like I am not able to exploit python for writing synthesizable code.
>> >
>> > For example, here is a description of a Dual ported ram:
>> > https://gist.github.com/jck/00e016e0ff6baa0e7fbf
>> >
>> > As you can see, there seems to be a lot of repeated code. And
>> additionally,
>> > it feels like the way of handling variables(such as data_a, data_b  
>> rather
>> > than a list of two elements) is unelegent/unpythonic.
>>
>> You mean repeated code in the port list (function
>> arguments) and signals used?
>>
>> If this is mainly what you are talking about, not
>> being able to have higher data structures, there are
>> some options.  But some of this is limited by having
>> to convert to V*, where they don't support similar
>> constructs, so the conversion has to do a lot more
>> work.  But with that said, we do have a MEP for
>> interfaces (MEP-107) which I hope to address in 0.9-dev.
>>
>> In anticipation for MEP-107 implementation you can use
>> attributes that are signals but you need to locally reference
>> the signals, example:
>>
>>      def DualPortRam(clock, dpram_a, dpram_b):
>>
>>          (data_a,addr_a,
>>           we_a,q_a,) = dpram_a.get_signals()
>>          (data_b,addr_b,
>>           we_b,q_b,) = dpram_b.get_signals()
>>
>>          ...
>>
>> Here is an example of a project where I used this technique:
>> https://github.com/cfelton/minnesota
>> https://groups.google.com/forum/#!topic/fpgalink-users/P8q7texZqIQ
>>
>> In the future if we implement the interfaces you will be
>> able to use /dpram_a.data/ directly.
>>
>> > Are there any python/myhdl techniques I could use to make this code  
>> more
>> > elegant? Additionally, I would like to see your code examples where  
>> you
>> > feel like the myhdl description is more elegant than conventional  
>> hdls,
>> > either in single modules, or a systems of interconnected modules.
>>
>> For me I see the biggest gain when I am writing very
>> parameterizable modules and more complicated modules,
>> where it is hard to envision how these might even look
>> in V*.  It typically includes a fair amount of computation
>> code in the elaboration phase, a small example from
>> DesignWest:
>>
>>
>> https://bitbucket.org/cfelton/dw2013_examples/src/tip/iir_filter/iir_type1.py
>>
>>
>> Regards,
>> Chris
>>
>>
>>
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>
>
>


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