Re: [myhdl-list] timescale in _toVerilog and cosimulation

[Christopher F. <chr...@gm...>]

On 4/26/2013 2:03 PM, Jos Huisken wrote:
> In a cosimulation (with icarus in this case) you can generate 2 .vcd files,
> one from myhdl and one from icarus (using $dumpfile).
> When viewing both using gtkwave the clock period is x10 different.
> I think this is caused by the `timescale 1ns/10ps directive in generated
> verilog. At least when replacing it by 1ns/1ps solves the issue.
>
> Is this the way to do it?
>
> -- Jos
>

Hmm, Icarus should use what is defined by the timescale
for the VCD creation?  There is a mismatch with the timescale
for the Verilog simulator and the timescale used in the
MyHDL VCD creation.

You can use the following to control the timescales in
MyHDL.

     traceSignals.timescale = '1ps'
     tb_dut = traceSignals(...)
     ...
     toVerilog.timescale = '1ns/1ps'
     toVerilog(...)

In addition there should be away to tell the Verilog
simulator what the time resolution is.  If you can't
control the time resolution with the above you might
want to look at adding it to the simulation command
(i don't recall what it is off the top of my head).

Regards,
Chris Felton