[myhdl-list] timescale in _toVerilog and cosimulation

[Jos H. <jos...@gm...>]

In a cosimulation (with icarus in this case) you can generate 2 .vcd files, 
one from myhdl and one from icarus (using $dumpfile).
When viewing both using gtkwave the clock period is x10 different.
I think this is caused by the `timescale 1ns/10ps directive in generated 
verilog. At least when replacing it by 1ns/1ps solves the issue.

Is this the way to do it?

-- Jos