Re: [myhdl-list] Keep hierarchy in VHDL conversion

[Oscar D. D. <osc...@gm...>]

El Sun, 14 Apr 2013 17:25:45 +0200
Angel Ezquerra <ang...@gm...> escribió:

> This is something I have wanted pretty much since I discovered MyHDL.
> I hope you can make all the tests pass soon and that you can implement
> the Verilog side as well. I also hope Jan can have a look and
> hopefully integrate it into the official MyHDL code base.

Well, my initial plan is to use it as a external module, and when it's
sufficiently stable (and proven useful to users), then merge with
default converters.

So I'm pursuing two approaches: the external module and patched
converters.

By the way, I know this should be in a MEP, I'll write it this week.

> 
> I went though the github readme file briefly, and it was not super
> clear to me how you select the output file names and who you create
> the corresponding entities. It would be nice if you had some example
> so that it was easier to understand how the whole thing works.

I uploaded a couple regression tests, but I think they can be used for
demonstration, also I attach another example (extracted from one of
the tests): convert_kh.py .

To answer your question: entity names are based on function names, and
each function call will generate an instance statement. However, it
checks argument values for each function call to decide how many
components to generate. That means any constants (analogous to generics
in VHDL) and bit-widths are hard-coded in components, but if you
instantiate many components with the same constants and bit-widths it
only generate one component.

>

Regarding existing regression tests, there's some tests that I cannot
pass due to VHDL errors (two of them fails with current snapshot):

1. some tests fails due to VHDL case-insensitive identifiers. What
should the correct procedure in this case? Either notify the user about
identifier conflicts, or change generated names to avoid them?

2. User-defined code cannot infer "inout" signals, and those tests
fails when attempt to read "out" signals. Here I don't know how to do
that without parsing user-defined code.

I also attach a summary with the problems I found
(regression_tests_summary.py) and test reports for the failed tests in
current snapshot.

> 
> Cheers,
> 
> Angel
> 

Best regards,
-- 
Oscar Díaz
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