Re: [myhdl-list] two issues about conversion

[Christopher F. <chr...@gm...>]

On 4/19/13 1:00 AM, Christopher Felton wrote:
> On 4/15/13 1:20 PM, David Guerrero Martos wrote:
>> Hello, my name is David and I'm new to MyHDL. I'm starting to learn
>> MyHDL and I've installed 0.8-dev. As an exercise, I'm trying to describe
>> and test an LFSR that is  attached as LFSR9.py. I got no errors when
>> executing it, but I cannot synthesize it because the code is not
>> properly converted to Verilog: If you have a look to the attached LFSR.v
>> you will see that the input to the xor gate is formed by references to
>> the name of the external variable passed as parameter (my_state) instead
>> of the formal name of the parameter in the prototype of the function
>> (state).
>>
>
> This one is a little tricky, I don't know the root
> cause or if it is an issue but I have duplicated the
> scenario  you have observed.  It will be some time before
> I can dig into this and see what the issue might be?
>
> I can offer a separate solution (see below/attached).
>
> Regards,
> Chris
>

from myhdl import *

def m_lfsr(clock,reset,prn,taps,N=3,initval=None):
     """ Simple Galois (one-to-many) LFSR

     Characteristic Polynomial Mapping
     ---------------------------------
     To define the LFSR sequence a "characteristic" polynomial
     is required.  This modules expects the polynomial described
     by the "taps" list.  The taps list is the delay elements
     that feed an XOR in a Galois LFSR configuration.

     The "taps" list is expanded into a bit position in the same
     word size as the lfs-register, then a loop can be used to
     insert the xors on the correct taps.
     """

     initval = (2**N)-1 if intval is None else initval
     # convert from compact form to expanded
     itaps = [Signal(bool(1)) if ii in taps else Signal(bool(0))
              for ii in range(N)]
     taps = Signal(concat(*itaps))
     lfsr = Signal(intbv(initval)[N:])

     @always_seq(clock.posedge, reset=reset)
     def hdl_lfsr():
         lfsr.next[0] = lfsr[N-1]
         for ii in range(1,N):
             if taps[ii-1]:
                 lfsr.next[ii] = lfsr[ii-1] ^ lfsr[N-1]
             else:
                 lfsr.next[ii] = lfsr[ii-1]

     if len(prn) == 1:
         @always_comb
         def hdl_out():
             prn.next = lfsr[N-1]
     else:
         @always_comb
         def hdl_out():
             prn.next = lfsr

     return hdl_lfsr,hdl_out


if __name__ == '__main__':
     clock = Signal(bool(0))
     reset = ResetSignal(0,active=0,async=False)
     prn = Signal(bool(0))
     taps = [0,2]
     toVerilog(m_lfsr,clock,reset,prn,taps=taps)