Re: [myhdl-list] two issues about conversion

[Christopher F. <chr...@gm...>]

On 4/15/13 1:20 PM, David Guerrero Martos wrote:
> Hello, my name is David and I'm new to MyHDL. I'm starting to learn
> MyHDL and I've installed 0.8-dev. As an exercise, I'm trying to describe
> and test an LFSR that is  attached as LFSR9.py. I got no errors when
> executing it, but I cannot synthesize it because the code is not
> properly converted to Verilog: If you have a look to the attached LFSR.v
> you will see that the input to the xor gate is formed by references to
> the name of the external variable passed as parameter (my_state) instead
> of the formal name of the parameter in the prototype of the function
> (state).
>

This one is a little tricky, I don't know the root
cause or if it is an issue but I have duplicated the
scenario  you have observed.  It will be some time before
I can dig into this and see what the issue might be?

I can offer a separate solution (see below/attached).

Regards,
Chris