[myhdl-list] two issues about conversion

[David G. M. <gu...@dt...>]

Hello, my name is David and I'm new to MyHDL. I'm starting to learn 
MyHDL and I've installed 0.8-dev. As an exercise, I'm trying to describe 
and test an LFSR that is  attached as LFSR9.py. I got no errors when 
executing it, but I cannot synthesize it because the code is not 
properly converted to Verilog: If you have a look to the attached LFSR.v 
you will see that the input to the xor gate is formed by references to 
the name of the external variable passed as parameter (my_state) instead 
of the formal name of the parameter in the prototype of the function 
(state).


The second issue I found while learning MyHDL was relative to shadow 
sliced signals. I attach another file with an example of it 
(reduce_and.py) . If I use an slice of just one bit, It works as I 
expect. But if the width of the slice is wider than one bit, I have to 
assign it to another intermediate signal in an always_comb generator to 
make it have any effect. Otherways, I will get a wrong conversion to 
Verilog. In the given example, if you change the reference to others in 
line 23 for its actual value [A(len(A),1)], it doesn't work, but if I 
use straight references to one-bit slices, as in lines 25 and 28, it 
does work as I'd expect in the previous case. Am I misunderstanding 
anything about shadow sliced signal or I hit a bug in the converter? I 
couldn't find any more info or examples about this kind of usecases in 
the documentation, sorry If I missed something.

Kind regards,
David.