Re: [myhdl-list] Keep hierarchy in VHDL conversion

[Angel E. <ang...@gm...>]

On Sun, Apr 14, 2013 at 3:54 AM, Oscar Daniel Diaz <osc...@gm...> wrote:
> Hi
>
> I've been working in this for a long time ago, and I managed to hack
> the converter to keep hierarchy as close as possible to MyHDL source
> design. Now, after a lot of code cleaning and passing almost all the
> tests I can release the code.
>
> https://github.com/dargor0/myhdl-addons
>
> check the "conversion" directory.
>
> Long threads and many words we have dedicated to this issue, but I want
> to re-state my motivation and main rationale to propose this "modified
> converter": It's very difficult to do floor-planning with a flat
> single-file design, not to mention almost impossible to do partial
> re-configuration (PR). With this converter, now I can generate a
> top-module based on component instantiations that reflects as close as
> possible the structural design from design source.
>
> This converter pass almost all regression tests (I'm working to pass
> all of them), but it is usable and works perfectly for its main
> use-case: keeping top-module structural design.
>
> Only VHDL conversion is supported for now, but I'm working on Verilog
> converter too.
>
> And finally, now that I propose this converter, I'd like to propose an
> Idea to extend conversion process. Following this proposal, I'm
> thinking of add custom "filter" functions to modify the extracted
> internal data (ast tree), and doing some kind of optimizations. It only
> needs one dummy function call in conversion code, then "custom
> converters" only need to subclass them. This initially would help me to
> avoid some monkey-patching I did to implement this converter, but I
> think it can be a starting point to extend the convertible subset, and
> also to ease testing of this "extensions".
>
> Best regards,
>
> --
> Oscar Díaz

Oscar, this is awesome!

This is something I have wanted pretty much since I discovered MyHDL.
I hope you can make all the tests pass soon and that you can implement
the Verilog side as well. I also hope Jan can have a look and
hopefully integrate it into the official MyHDL code base.

I went though the github readme file briefly, and it was not super
clear to me how you select the output file names and who you create
the corresponding entities. It would be nice if you had some example
so that it was easier to understand how the whole thing works.

Cheers,

Angel