Re: [myhdl-list] Missing parens in isinstance call, in _toVHDL.py

[Jan D. <ja...@ja...>]

Thanks.

This was a duplicate of bug 28 that I forgot to solve
(also for lack of a test case.)

I have solved it now in the default branch and 0.8-dev.

On 03/28/2013 09:04 PM, Thomas Heller wrote:
> The following diff is against the current 0.8-dev branch.
> The bug is triggered when code like this is converted:
>
>       dout.next = 0x8030 + (channel << 10)
>
> Thomas
>
>
> diff -r 57a3b8fd0e77 myhdl/conversion/_toVHDL.py
> --- a/myhdl/conversion/_toVHDL.py       Sun Mar 10 22:25:20 2013 +0100
> +++ b/myhdl/conversion/_toVHDL.py       Thu Mar 28 21:01:14 2013 +0100
> @@ -602,7 +602,7 @@
>                    else:
>                        raise AssertionError("unexpected op %s" % op)
>                elif isinstance(left.vhd, vhd_int) and
> isinstance(right.vhd, vhd_vector):
> -                if isinstance(op, ast.Add, ast.Sub, ast.Mod, ast.FloorDiv):
> +                if isinstance(op, (ast.Add, ast.Sub, ast.Mod,
> ast.FloorDiv)):
>                        right.vhd.size = ns
>                        node.vhdOri.size = ns
>                    elif isinstance(op, ast.Mult):
>
>
> ------------------------------------------------------------------------------
> Own the Future-Intel(R) Level Up Game Demo Contest 2013
> Rise to greatness in Intel's independent game demo contest. Compete
> for recognition, cash, and the chance to get your game on Steam.
> $5K grand prize plus 10 genre and skill prizes. Submit your demo
> by 6/6/13. http://altfarm.mediaplex.com/ad/ck/12124-176961-30367-2
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com