[myhdl-list] Keep hierarchy in VHDL conversion

[Oscar D. D. <osc...@gm...>]

Hi

I've been working in this for a long time ago, and I managed to hack
the converter to keep hierarchy as close as possible to MyHDL source
design. Now, after a lot of code cleaning and passing almost all the
tests I can release the code.

https://github.com/dargor0/myhdl-addons

check the "conversion" directory. 

Long threads and many words we have dedicated to this issue, but I want
to re-state my motivation and main rationale to propose this "modified
converter": It's very difficult to do floor-planning with a flat
single-file design, not to mention almost impossible to do partial
re-configuration (PR). With this converter, now I can generate a
top-module based on component instantiations that reflects as close as
possible the structural design from design source.

This converter pass almost all regression tests (I'm working to pass
all of them), but it is usable and works perfectly for its main
use-case: keeping top-module structural design.

Only VHDL conversion is supported for now, but I'm working on Verilog
converter too.

And finally, now that I propose this converter, I'd like to propose an
Idea to extend conversion process. Following this proposal, I'm
thinking of add custom "filter" functions to modify the extracted
internal data (ast tree), and doing some kind of optimizations. It only
needs one dummy function call in conversion code, then "custom
converters" only need to subclass them. This initially would help me to
avoid some monkey-patching I did to implement this converter, but I
think it can be a starting point to extend the convertible subset, and
also to ease testing of this "extensions".

Best regards,

-- 
Oscar Díaz
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