Re: [myhdl-list] Bug in generated code?

[Thomas H. <th...@ct...>]

Am 24.02.2013 21:51, schrieb Jan Decaluwe:
> On 01/17/2013 11:23 PM, Thomas Heller wrote:
>> Am 17.01.2013 17:26, schrieb Tom Dillon:
>>> Hi,
>>>
>>> This is interesting but I don't think it would be a bug. I am not sure
>>> the MyHDL specs call for automatic size conversions.
>>
>> I'd say it is a bug, because the generated VHDL code behaves differently
>> than the MyHDL simulation.
>
> That is correct - no excuses. If the conversion succeeds, the VHDL
> should be have as the VHDL, otherwise it's a bug.
>
> Of course, this doesn't mean that it would be easy to fix :-)
>
> However, I think the issue you reported is fixed now in development.

Thanks, Jan, for confirming that my understanding of MyHDL is correct.
And thanks for fixing the problem of course.  I'll try it out when I get
back to my project again.

Thomas