Re: [myhdl-list] intbv with max != 2**n. Error or annoyance?

[Christopher F. <chr...@gm...>]

On 2/25/2013 10:23 AM, Jan Decaluwe wrote:
> Chris:
>
> We are overthinking this. Forget about delta cycles,
> combinatorial logic and race conditions.

Fair enough.

>
> What we have is a language that hopefully tries to
> help us to write better, clearer code.
>
> A signal assignment is an assignment also (albeit
> to a future value which may or may not be overwritten.)
> When a designer specifies explicitly that a variable/signal
> should *always* be within a range that he specifies,
> it is a good thing that the language flags a
> violation immediately. The fact that signals have
> complex postponed behavior is a secondary issue.
>
> What disturbs me a little in this discussion is the
> Verilog angle. I think it is rather clear that
> VHDL is my reference for "good design" (and Verilog
> for "very bad design"). No?

It was inadvertent.  It was not the goal to imply myhdl
should behave like Verilog.  The oversight was --as you
identified-- not jumping to the VHDL example using a similar
type, that is: the constraint integer.

I am in agreement but I may beat on this topic some more,
purely so that I have a consistent and concise understanding
for future communications.

Regards,
Chris