Re: [myhdl-list] myhdl + qucs

[Christopher F. <chr...@gm...>]

On 2/17/13 12:22 PM, Todd Greenwood-Geer wrote:
> I'm new to EE, and trying to learn analog, digital, + vhdl. I don't have
> any hardware, so I'm trying this all via open source digital toolkits.
>
> My real attempt at this is to take a simple myhdl snippet (the
> incrementer here
> http://www.myhdl.org/doc/current/manual/conversion_examples.html),
> generate the VHDL, and then insert that into a QUCS project. Why? Well,
> I'd like to generate simple VHDL components, and then test them in a
> real circuit with things like transistors and mosfets and whatnot. If
> there is a better path to this, please speak up :).
>
> My issue is that QUCS (via freeHDL) rewrites the vhdl to a different
> directory, and then chokes on the include file generated by myHDL.
>
> // import line chokes on 'work' in QUCS/freeHDL
> use work.pck_myhdl_07.all;
>
> // error
>   >>> work.pck_myhdl_07 is undeclared
>
> Now, these are clearly not myHDL issues. However, I've tried various
> things to work around this...copying the include file into the target
> vhdl, copying the include file next to the source vhdl file, etc. So, my
> questions are:
>
> 1. Is there a way to tell myHDL to just generate a single VHDL output file?

Not that I am aware of.  This would be a reasonable request to
embedded the functions in the architecture for single file use
cases but it would probably be awhile before someone could get
around to making the enhancement.

>
> 2. Is there a better tool chain for learning all this stuff?
>
> Thanks!
>

This might be of interest, 
http://www.myhdl.org/doku.php/projects:mixedmodesimulation

Another MyHDL user created an example connecting eispice
(Python wrapper around spice) and MyHDL.  eispice is not as
full featured as qucs but it might be enough to do what you
want.  And you get the benefit of doing everything in Python!

Regards,
Chris