[myhdl-list] A puzzling error

[garyr <ga...@fi...>]

Below is a portion of the code for a multiplier module that works fine in its
test bench. It also worked OK as part of a lowpass filter module; that is, the
filter module test bench didn't reveal any problems. But when the filter module
is converted to Verilog an error occurs. The -547 is the value assigned to
signal 'multiplier'. As you can see it wasn't negated properly; instead of
(--547) it should be (547). Is this a bug or have I screwed up somewhere?

        elif start == ACTIVE_LOW:
            done.next = INACTIVE_HIGH
            result.next = 0
            if multiplier >= 0:
                mpyVar.next = multiplier
                negate.next = 0
            else:
                mpyVar.next = -multiplier
                negate.next = 1

    else if ((FA_FO_startm == 0)) begin
        FA_FO_donem <= 1;
        FA_FO_result <= 0;
        if ((-547 >= 0)) begin
            FA_FO_MPY_mpyVar <= -547;
            FA_FO_MPY_negate <= 0;
        end
        else begin
            FA_FO_MPY_mpyVar <= (--547);
            FA_FO_MPY_negate <= 1;
        end