[myhdl-list] MyHDL comments in a Workshop

[Christopher F. <chr...@gm...>]

Recently, I burned the midnight oil to watch some
presentations at [1].  The group is looking at
alternatives to replace their Matlab/Simulink FPGA
configurations for their "seti" like projects.
The SKA group works with (alongside, competes?) the
CASPER folks [2].

An item in a presentation needs correcting.  At one
point a presenter was talking about MyHDL and he
indicated MyHDL does one-to-one conversion, the MyHDL
source to the converted source.  This is not entirely
true, MyHDL has an "elaboration" phase.  In the
elaboration there is a lot of power to be utilized if
one desires.  The description in the generator will be
one-to-one (or close to).  The one-to-one comment was
incorrect in the context and misleading.

One example is Norbo's recent low resource FFT
implementation [3].

Regards,
Chris

[1] https://sites.google.com/site/hpdspworkshopcpt2012/home
[2] https://casper.berkeley.edu/
[3] 
http://article.gmane.org/gmane.comp.python.myhdl/2976/match=re+low+resource+fft+core+myhdl+first+python+modell