Re: [myhdl-list] tristates and inout ports at the top level

[Christopher F. <chr...@gm...>]

On 2/11/2013 10:11 AM, garyr wrote:
>
> ----- Original Message -----
> From: "Christopher Felton" <chr...@gm...>
> To: <myh...@li...>
> Sent: Thursday, February 07, 2013 9:29 AM
> Subject: Re: [myhdl-list] tristates and inout ports at the top level
>
>
>> On 2/7/2013 11:18 AM, Christopher Felton wrote:
>>> On 2/7/2013 10:00 AM, Jose Ignacio Villar wrote:
>>>> Hi all!
>>>> First of all I'd like to apologise if this subject has already been
>>>> discussed.  I googled and searched this mailing list for a solution to my
>>>> problem and I couldn't find any answer to it.
>>>> It is about tristates in the top level of my design. Is it possible in
>>>> MyHDL?
>>>> I have integrated a memory controller which one of his ports is
>>>> input/output, and it has to reach outside of the top level since it is used
>>>> to communicate with the off-chip memory. The integration of this controller
>>>> is done through user defined verilog code.
>>>> I read the toVerilog converter but i couldn't find any place where inout
>>>> ports are generated.
>>>>
>>>> Thanks in advance,
>>>> Jose.
>>>>
>>>
>>> This thread/example might help:
>>> http://thread.gmane.org/gmane.comp.python.myhdl/2224/focus=2227
>>>
>>> Regards,
>>> Chris
>>>
>>>
>>
>> Looking at the thread I posted a little closer it might
>> not be what you want.  In the thread they simply resolved
>> the simulation - behavior - of a bidirectional bus.  You
>> are looking for a conversion method.
>>
>> Best of my knowledge there is no support for tri-states.
>> The most common solution is to write a very thin wrapper
>> in Verilog/VHDL to handle the tri-state portion.  There
>> probably is some slick way to keep in all in Python/MyHDL
>> using the <hdl_module>.verilog_code attribute but I have
>> not tried it.
>>
>> Regards,
>> Chris
>
> The following is the code I used to implement a bidirectional bus for a USB
> device (FT245R). I don't pretend to fully understand it all; I arrived at this
> after receiving suggestions from several posts to one of the Altera forums. No
> doubt it could be done in a more elegant manner. Unfortunately the declaration
> of the bidirectional bus signal in the generated Verilog file must be changed
> from output to inout.
>
<snip code>

Thanks for posting this example,

I think something like this should be the general
solution for tri-states (and other device specific
functions, not that tri-state is device specific).

As you elude, we should add to the converters to
detect a /TristateSignal/ at the top-level and
write and /inout/ instead of /in/ or /out/.

Regards,
Chris