Re: [myhdl-list] tristates and inout ports at the top level

[garyr <ga...@fi...>]

----- Original Message ----- 
From: "Christopher Felton" <chr...@gm...>
To: <myh...@li...>
Sent: Thursday, February 07, 2013 9:29 AM
Subject: Re: [myhdl-list] tristates and inout ports at the top level


> On 2/7/2013 11:18 AM, Christopher Felton wrote:
>> On 2/7/2013 10:00 AM, Jose Ignacio Villar wrote:
>>> Hi all!
>>> First of all I'd like to apologise if this subject has already been
>>> discussed.  I googled and searched this mailing list for a solution to my
>>> problem and I couldn't find any answer to it.
>>> It is about tristates in the top level of my design. Is it possible in
>>> MyHDL?
>>> I have integrated a memory controller which one of his ports is
>>> input/output, and it has to reach outside of the top level since it is used
>>> to communicate with the off-chip memory. The integration of this controller
>>> is done through user defined verilog code.
>>> I read the toVerilog converter but i couldn't find any place where inout
>>> ports are generated.
>>>
>>> Thanks in advance,
>>> Jose.
>>>
>>
>> This thread/example might help:
>> http://thread.gmane.org/gmane.comp.python.myhdl/2224/focus=2227
>>
>> Regards,
>> Chris
>>
>>
>
> Looking at the thread I posted a little closer it might
> not be what you want.  In the thread they simply resolved
> the simulation - behavior - of a bidirectional bus.  You
> are looking for a conversion method.
>
> Best of my knowledge there is no support for tri-states.
> The most common solution is to write a very thin wrapper
> in Verilog/VHDL to handle the tri-state portion.  There
> probably is some slick way to keep in all in Python/MyHDL
> using the <hdl_module>.verilog_code attribute but I have
> not tried it.
>
> Regards,
> Chris
>
>
>
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The following is the code I used to implement a bidirectional bus for a USB
device (FT245R). I don't pretend to fully understand it all; I arrived at this
after receiving suggestions from several posts to one of the Altera forums. No
doubt it could be done in a more elegant manner. Unfortunately the declaration
of the bidirectional bus signal in the generated Verilog file must be changed
from output to inout.

def usbIO(clk, TXE, RXF, RD, WR, rxbyte, txbyte, usbbus):
    @always(clk.negedge)
    def logic():
        pass
    TXE.read = True
    RXF.read = True
    RD.read = True
    WR.read = True
    rxbyte.driven = "wire"
    txbyte.read = True
    usbbus.driven = "wire"      # must be changed to inout in usbIO.v.
    return logic
usbIO.verilog_code = \
"""
/*
    TXE     -   Write enable
    WR      -   Write strobe
    RXF     -   Read enable, active low
    RD      -   Read strobe, active low
    rxbyte  -   Byte received from device
    txbyte  -   Byte to be transmitted to device
    usbbus  -   Bidirectional I/O bus

input clk, TXE, RXF, RD, WR;
input [7:0] txbyte;
output [7:0] rxbyte;
inout [7:0] usbbus;
*/
reg [7:0] usbbusEn, rxbyteIn;
assign $rxbyte = rxbyteIn;
assign $usbbus = usbbusEn;

    always @ (negedge $clk) begin
        if (~$RXF & ~$RD)
            rxbyteIn <= $usbbus;

        if (~$TXE & $WR)
            usbbusEn <= $txbyte;

        if ($TXE == 1)
            usbbusEn <= 8'bz;
    end
"""