[myhdl-list] tristates and inout ports at the top level

[Jose I. V. <jo...@dt...>]

Hi all!
First of all I'd like to apologise if this subject has already been
discussed.  I googled and searched this mailing list for a solution to my
problem and I couldn't find any answer to it.
It is about tristates in the top level of my design. Is it possible in
MyHDL?
I have integrated a memory controller which one of his ports is
input/output, and it has to reach outside of the top level since it is used
to communicate with the off-chip memory. The integration of this controller
is done through user defined verilog code.
I read the toVerilog converter but i couldn't find any place where inout
ports are generated.

Thanks in advance,
Jose.


José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)