Re: [myhdl-list] VHDL Conversion Errors

[Christopher F. <chr...@gm...>]

On 1/26/13 8:30 PM, Christopher Felton wrote:
> <snip>
>>
>>           1 = /if not reset/
>>           2 = /reset == False/
>>           3 = /reset == bool(0)/
>>           4 = /reset == 0/
>>           5 = /reset == intbv(0)/
<snip>
>
> Norbo, thanks for posting this.  I think we got
> a little off track with this "issue", which I don't
> think is an issue.  The errors we were seeing were with
> the special case of *reset*.  As you demonstrated the
> different conditional statements work fine (except case 5).
> It is only the *reset* case that raises some questions with
> VHDL conversion or more generally an edge sensitive signal
> other than a clock.
>
> In the manual [1] Jan calls out /reset == 0/.  I think this
> is ok to require this for the reset cases.  It can be an
> enhancement to add /reset == False/ but I don't think it
> is a bug and I think it would be low priority enhancement.
> Since the four cases work fine in the other uses, I don't
> see the *reset* case being much worry, especially since we
> can use the /@always_seq/ with the latest 0.8dev.
>

Here is Jan's earlier response on this topic:
http://article.gmane.org/gmane.comp.python.myhdl/2773/match=logical+interpretation

Regards,
Chris