Re: [myhdl-list] intbv with max != 2**n. Error or annoyance?

[Per K. <bas...@gm...>]

OK, the range check is essentially an assertion. Now, you wouldn't put an
assertion in a combinatorical block, would you?

So the least you can expect is a warning message that you got one when you
used an intbv with ranges != 2**n as a combinatorical net.

Don't worry, otherwise I like intbv as much as the next guy!
/Per

ps. It behaves the same in 0.7 and 0.8-dev.



On Tue, Jan 29, 2013 at 12:55 PM, Christopher Felton <chr...@gm...
> wrote:

> On 1/28/13 10:01 AM, Per Karlsson wrote:
> > Hm.
> > Let's say the flag computation is something a lot more complex, and the
> > flag is used in a lot of places. Then the verilog is going to be more
> > compact, easier to maintain and less error prone.
> > Why then would we want myhdl?
> >
> > Also, who says you have control over the flag computation? Perhaps it is
> > a combinatorical output from an IP.  (A myhdl IP of course!)
> >
> > I think we need to root out all those instances where verilog makes more
> > sense than myhdl, or designers will stick with verilog.
> > /Per
> >
>
>
> Ignoring the specific bound check race condition for the
> moment, simply because Jan D. would have better insight than
> me, I need to take some time and ponder.
>
> Only considering "instances where Verilog makes more sense
> than myhdl" proposition. This can be difficult because in
> most cases it is, somewhat, subjective and biased on our
> past experiences. In Verilog I can do the following all
> day long:
>
>      wire [7:0] y;
>      reg [2:0] x;
>      assign y = 27;
>      always @* begin  // or always_comb
>          x = y;
>      end
>
> Not so much in VHDL and in MyHDL I cannot:
>
>     y = Signal(intbv(27, min=0, max=256))
>     x = Signal(intbv(0, min=0, max=4))
>     @always_comb
>     def hdl():
>        x.next = y
>
> Someone might like the Verilog version because  they
> implicitly want the behavior - chop it -.  I think most
> agree the /intbv/ is a nice abstraction (see [1]).
> But if you are use to the rules and behavior of Verilog
> it might be hard to break the habit :)
>
> I realize I digressed a bit.  Back to the problem reported.
> I want to test this failure with 0.7 and see if it is
> something new or something that has been around.  More to
> come ...
>
> Regards,
> Chris Felton
>
> [1] http://www.jandecaluwe.com/hdldesign/counting.html
> [2]
>
> https://bitbucket.org/cfelton/myhdl_tests/src/tip/test_bound_race.py?at=default
>
>
>
>
>
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