Re: [myhdl-list] VHDL Conversion Errors

[Christopher F. <chr...@gm...>]

<snip>
>
>          1 = /if not reset/
>          2 = /reset == False/
>          3 = /reset == bool(0)/
>          4 = /reset == 0/
>          5 = /reset == intbv(0)/
>
>         simulation:
> 	all pass
>
>         vhdl:
>          1 converted vhdl, ok
>          2 converted vhdl, ok
>          3 converted vhdl, ok
>          4 converted vhdl, ok
>          5 converted vhdl, no warning given, converted code is not correct.

Norbo, thanks for posting this.  I think we got
a little off track with this "issue", which I don't
think is an issue.  The errors we were seeing were with
the special case of *reset*.  As you demonstrated the
different conditional statements work fine (except case 5).
It is only the *reset* case that raises some questions with
VHDL conversion or more generally an edge sensitive signal
other than a clock.

In the manual [1] Jan calls out /reset == 0/.  I think this
is ok to require this for the reset cases.  It can be an
enhancement to add /reset == False/ but I don't think it
is a bug and I think it would be low priority enhancement.
Since the four cases work fine in the other uses, I don't
see the *reset* case being much worry, especially since we
can use the /@always_seq/ with the latest 0.8dev.

I had created some tests [2] and added combinatorial and
sequential conditionals.  As discussed all four cases
convert unless used as a reset, reset has to be explicitly
/reset == 0/ or /reset == 1/ (or use @always_seq).

The last case , case 5, I think will fall under the general
mixing of /bool/ and /intbv[1:]/.  I am going to remove the
conditional from the short list of bugs that I am keeping.

Here is the summary from the tests I ran and can be found
at [2].  Like I said, I think we should remove this one
from the "bug" list (low priority and is document how
the modeling is expected).  The biggest issue would be
the mismatch in MyHDL simulation and Verilog conversion.
My cases are the same as you enumerated, we could have
removed case 3 it is the same as 2.

    myhdl   :test_ifnot_comb_1: success
    ghdl    :test_ifnot_comb_1: success
    icarus  :test_ifnot_comb_1: success

    myhdl   :test_ifnot_comb_2: success
    ghdl    :test_ifnot_comb_2: success
    icarus  :test_ifnot_comb_2: success

    myhdl   :test_ifnot_comb_3: success
    ghdl    :test_ifnot_comb_3: success
    icarus  :test_ifnot_comb_3: success

    myhdl   :test_ifnot_comb_4: success
    ghdl    :test_ifnot_comb_4: success
    icarus  :test_ifnot_comb_4: success

    myhdl   :test_ifnot_comb_5: success
    ghdl    :test_ifnot_comb_5: failed
    icarus  :test_ifnot_comb_5: success

    myhdl   :test_ifnot_reset_1: success
    ghdl    :test_ifnot_reset_1: failed
    icarus  :test_ifnot_reset_1: success

    myhdl   :test_ifnot_reset_2: success
    ghdl    :test_ifnot_reset_2: failed
    icarus  :test_ifnot_reset_2: success

    myhdl   :test_ifnot_reset_3: success
    ghdl    :test_ifnot_reset_3: failed
    icarus  :test_ifnot_reset_3: success

    myhdl   :test_ifnot_reset_4: success
    ghdl    :test_ifnot_reset_4: success
    icarus  :test_ifnot_reset_4: success

    myhdl   :test_ifnot_reset_5: success
    ghdl    :test_ifnot_reset_5: failed
    icarus  :test_ifnot_reset_5: success

    myhdl   :test_ifnot_seq_1: success
    ghdl    :test_ifnot_seq_1: success
    icarus  :test_ifnot_seq_1: success

    myhdl   :test_ifnot_seq_2: success
    ghdl    :test_ifnot_seq_2: success
    icarus  :test_ifnot_seq_2: success

    myhdl   :test_ifnot_seq_3: success
    ghdl    :test_ifnot_seq_3: success
    icarus  :test_ifnot_seq_3: success

    myhdl   :test_ifnot_seq_4: success
    ghdl    :test_ifnot_seq_4: success
    icarus  :test_ifnot_seq_4: success

    myhdl   :test_ifnot_seq_5: success
    ghdl    :test_ifnot_seq_5: failed
    icarus  :test_ifnot_seq_5: success

Regards,
Chris

[1] http://www.myhdl.org/doc/current/manual/modeling.html#sequential-logic

[2] 
https://bitbucket.org/cfelton/myhdl_tests/src/tip/test_ifnot.py?at=default