Re: [myhdl-list] VHDL Conversion Errors

[Norbo <Nor...@gm...>]

Am 23.01.2013, 20:15 Uhr, schrieb Christopher Felton
<chr...@gm...>:

> On 1/23/2013 10:35 AM, Norbo wrote:
>>> On the #2 issues, since the MyHDL simulation != VHDL
>>> simulation, does this constitute an error, not sure?  I
>>> had a similar issue, I often used:
>>>
>>>          if reset:
>>>
>>> The myhdl simulation worked and Verilog conversion worked
>>> but the VHDL did not, the fix was to explicitly state:
>>>
>>>          if reset == False:
>>>
>>> Even though there was a simulation mismatch it was suggested
>>> that the "reset == False", is the desired form.  I am not sure
>>> if the mixed type comparison should be converted?  Instead, we
>>> probably want the converter to raise a conversion exception and
>>> not convert the code.
>>
>> i am a bit confused:
>> when a negedge event on the reset is inserted in the sensitivity list,
>> then it would
>> look like the following, right?
>>
>> ############## case 1 ###########
>>
>>       if reset:
>>
>> -->> conversion to vhdl works but would be the wrong value for the  
>> negedge
>> event. right?
>>
>>
>>
>> ############## case 2 ###########
>>
>>       if not reset:
>>
>> -->> conversion to vhdl fails, with: Error:  No proper edge value test
>>
>>
>> ############## case 3 ###########
>>
>>       if reset== False:
>>
>> -->> conversion to vhdl fails, with: Error:    No proper edge value test
>>
>>
>> ############## case 4 ###########
>>
>>       if reset== bool(0):
>>
>> -->> conversion to vhdl fails, with: Error:    No proper edge value test
>>
>>
>> ############## case 5 ###########
>>
>>       if reset==0:
>>
>> -->> The working version !!
>>
>>
>> greetings
>> Norbo
>>
>>
>
> Correct, if we create an example(s):
>
>     @always(clock.posedge, reset.negedge)
>     def hdl():
>        if reset == False:
>        ...
>
> The only version that appears to convert with 0.8 is the
> /reset == 0/?  That seems wrong?  I will have to try 0.7
> and think about this a little more.  Will need to get a
> bunch of caffeine for tonight :)  Unless anyone else has
> some insight?
>
> The results from the code snip below (same as Norbo's):
>
>     1 = /if not reset/
>     2 = /reset == False/
>     3 = /reset == bool(0)
>     4 = /reset == 0/
>
>     1 error vhdl in file tb_ifnot.py, line 8:
>         No proper edge value test
>     2 error vhdl in file tb_ifnot.py, line 17:
>         No proper edge value test
>     3 error vhdl in file tb_ifnot.py, line 26:
>         No proper edge value test
>     4 converted vhdl
>
>     1 converted verilog
>     2 converted verilog
>     3 converted verilog
>     4 converted verilog
>


The following is the result for an example which looks like this (when the
if is used in a combinatorical statement and
not as a reset):

       @always_comb
       def read():
         if reset==False:
	......
         else:
           ....


        1 = /if not reset/
        2 = /reset == False/
        3 = /reset == bool(0)/
        4 = /reset == 0/
        5 = /reset == intbv(0)/

       simulation:
	all pass

       vhdl:
        1 converted vhdl, ok
        2 converted vhdl, ok
        3 converted vhdl, ok
        4 converted vhdl, ok
        5 converted vhdl, no warning given, converted code is not correct.



here is the code:
#####################################

   from myhdl import *
def selecttry_1(reset,dout):
       @always_comb
       def read():
         if not reset:
	dout.next=5
         else:
           dout.next=6
       return read

def selecttry_2(reset,dout):
       @always_comb
       def read():
         if reset==False:
	dout.next=5
         else:
           dout.next=6
       return read

def selecttry_3(reset,dout):
       @always_comb
       def read():
         if reset==bool(0):
	dout.next=5
         else:
           dout.next=6
       return read


def selecttry_4(reset,dout):
       @always_comb
       def read():
         if reset==0:
	dout.next=5
         else:
           dout.next=6
       return read

def selecttry_5(reset,dout):
       @always_comb
       def read():
         if reset==intbv(0):
	dout.next=5
         else:
           dout.next=6
       return read

cases=[globals()[x] for x in dir() if "selecttry_" in x]


### simulating all cases
for func in cases:
     def testbench():
       sel=Signal(bool(0))
       dout=Signal(intbv(0)[8:])
       dut_inst=func(sel,dout)

       @instance
       def tb_stim():
           print 'Start sim of:',func.func_name,
           sel.next = False
           yield delay(10)
           assert dout==5
           sel.next = True
           yield delay(10)
           assert dout==6

           print ' sim completed'

           raise StopSimulation

       return dut_inst, tb_stim

     Simulation(testbench()).run()


## converting to VHDL with bool as select signal
sel=Signal(bool(0))
dout=Signal(intbv(0)[8:])
for index, func in enumerate(cases):
     try:
       toVHDL(func,sel,dout)
       print "Converting ",func.func_name, " completed"
     except:
       print "Error in ", func.func_name


greetings
Norbo