Re: [myhdl-list] VHDL Conversion Errors

[Christopher F. <chr...@gm...>]

On 1/24/2013 1:58 AM, Thomas Heller wrote:
> Am 23.01.2013 03:38, schrieb Christopher Felton:
>>
>> Let me try and summarize, we believe we have encountered
>> three different VHDL conversion errors.
>>
>>       1. bitwise multiplication (there was the wider
>>       question if the types were correct but since the ops
>>       were invalid it was a moot point).
>>
>>       2. An odd intbv(val) == bool(val) comparison error,
>>       python allows this check (what is the rule?) but when
>>       converted the mixed types is not a valid comparison?
>>
>>       3. More than two operand math operations and resizing.
>>
>> On the #2 issues, since the MyHDL simulation != VHDL
>> simulation, does this constitute an error, not sure?
>
> Same for +3.
>
> It would be nice to hear some 'official words' on that from Jan.
>

Yes of course, but we can help quite a bit by generating
unit tests (I think I have all these) and suggesting possible
fixes and/or reasons whey we think the *issues* we are observing
should be supported.

It is common for most of us, that our responsibilities fluctuate,
hence we are busier at certain times than others.  I think we can
help keep the ball moving forward by organizing these issues.

>>
>> Now, the best way to keep track of these so we don't loose
>> track of them?
>
> The general answer to this, of course, is to submit an item into
> the tracker (after discussion in this newsgroup).

The only question, the sourceforge tracker has never been used
(best of my knowledge).  Do we use the sourceforge tracker or ???

Regards,
Chris Felton