Re: [myhdl-list] AttributeError in 0.8-dev but not in 0.7
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From: Christopher F. <chr...@gm...> - 2013-01-24 13:48:25
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On 1/24/2013 5:49 AM, Per Karlsson wrote: > Hi! > I have dug a little deeper, and it has to do with using Signal(bool(False)) > and Signal(intbv(0)[1:0]). > If I use only the latter and make all comparisons explicit ("if flag==1" > instead of just "if flag") the AttributeError goes away. > I have also seen that even if I don't get the attribute error there are > simulation mismatches between the verilog and the myhdl when intbv and bool > are mixed. > > I've seen this discussed on the boards before, and I think it is obvious > that we need to support "if not flag:"-like syntax. It makes the code > easier to read, and it works in both python and verilog. > /Per > Thanks for the additional information but I still can't reproduce the error with 0.8-dev (ignoring conversion for now). If I understand correctly you are saying if you use /if Signal(intbv):/ and /if not Signal(intbv):/ it should cause the problem? The following little test, works: def test(): #flag = Signal(bool(0)) flag = Signal(intbv(0)[1:]) @instance def tb_stim(): print('myhdl version %s' % (myhdl.__version__)) print('start ...') for ii in range(3): if not flag: flag.next = not flag yield delay(10) print("%8d : %s" % (now(), repr(flag))) if flag: flag.next = not flag yield delay(10) print("%8d : %s" % (now(), repr(flag))) print('... end') return tb_stim produces: >>> Simulation(test()).run() myhdl version 0.8dev start ... 10 : Signal(intbv(True)) 20 : Signal(intbv(False)) 30 : Signal(intbv(True)) 40 : Signal(intbv(False)) 50 : Signal(intbv(True)) 60 : Signal(intbv(False)) ... end And I ran the same test with /flag = Signal(bool)/ and I did not observe an issue either? Regards, Chris Felton |