Re: [myhdl-list] VHDL Conversion Errors

[Thomas H. <th...@ct...>]

Am 23.01.2013 03:38, schrieb Christopher Felton:
>
> Let me try and summarize, we believe we have encountered
> three different VHDL conversion errors.
>
>      1. bitwise multiplication (there was the wider
>      question if the types were correct but since the ops
>      were invalid it was a moot point).
>
>      2. An odd intbv(val) == bool(val) comparison error,
>      python allows this check (what is the rule?) but when
>      converted the mixed types is not a valid comparison?
>
>      3. More than two operand math operations and resizing.
>
> On the #2 issues, since the MyHDL simulation != VHDL
> simulation, does this constitute an error, not sure?

Same for +3.

It would be nice to hear some 'official words' on that from Jan.

>
> Now, the best way to keep track of these so we don't loose
> track of them?

The general answer to this, of course, is to submit an item into
the tracker (after discussion in this newsgroup).

Thomas