Re: [myhdl-list] VHDL Conversion Errors

[Christopher F. <chr...@gm...>]

On 1/23/2013 10:35 AM, Norbo wrote:
>> On the #2 issues, since the MyHDL simulation != VHDL
>> simulation, does this constitute an error, not sure?  I
>> had a similar issue, I often used:
>>
>>          if reset:
>>
>> The myhdl simulation worked and Verilog conversion worked
>> but the VHDL did not, the fix was to explicitly state:
>>
>>          if reset == False:
>>
>> Even though there was a simulation mismatch it was suggested
>> that the "reset == False", is the desired form.  I am not sure
>> if the mixed type comparison should be converted?  Instead, we
>> probably want the converter to raise a conversion exception and
>> not convert the code.
>
> i am a bit confused:
> when a negedge event on the reset is inserted in the sensitivity list,
> then it would
> look like the following, right?
>
> ############## case 1 ###########
>
>       if reset:
>
> -->> conversion to vhdl works but would be the wrong value for the negedge
> event. right?
>
>
>
> ############## case 2 ###########
>
>       if not reset:
>
> -->> conversion to vhdl fails, with: Error:  No proper edge value test
>
>
> ############## case 3 ###########
>
>       if reset== False:
>
> -->> conversion to vhdl fails, with: Error:    No proper edge value test
>
>
> ############## case 4 ###########
>
>       if reset== bool(0):
>
> -->> conversion to vhdl fails, with: Error:    No proper edge value test
>
>
> ############## case 5 ###########
>
>       if reset==0:
>
> -->> The working version !!
>
>
> greetings
> Norbo
>
>

Correct, if we create an example(s):

    @always(clock.posedge, reset.negedge)
    def hdl():
       if reset == False:
       ...

The only version that appears to convert with 0.8 is the
/reset == 0/?  That seems wrong?  I will have to try 0.7
and think about this a little more.  Will need to get a
bunch of caffeine for tonight :)  Unless anyone else has
some insight?

The results from the code snip below (same as Norbo's):

    1 = /if not reset/
    2 = /reset == False/
    3 = /reset == bool(0)
    4 = /reset == 0/

    1 error vhdl in file tb_ifnot.py, line 8:
        No proper edge value test
    2 error vhdl in file tb_ifnot.py, line 17:
        No proper edge value test
    3 error vhdl in file tb_ifnot.py, line 26:
        No proper edge value test
    4 converted vhdl

    1 converted verilog
    2 converted verilog
    3 converted verilog
    4 converted verilog


Regards,
Chris

~~~ Code Snip ~~~
from myhdl import *
import subprocess

def ifnot_1(clock,reset,a,b):
     @always(clock.posedge, reset.negedge)
     def hdl():
         if not reset:
             b.next = False
         else:
             b.next = not a
     return hdl

def ifnot_2(clock,reset,a,b):
     @always(clock.posedge, reset.negedge)
     def hdl():
         if reset == False:
             b.next = False
         else:
             b.next = not a
     return hdl

def ifnot_3(clock,reset,a,b):
     @always(clock.posedge, reset.negedge)
     def hdl():
         if reset == bool(0):
             b.next = False
         else:
             b.next = not a
     return hdl

def ifnot_4(clock,reset,a,b):
     @always(clock.posedge, reset.negedge)
     def hdl():
         if reset == 0:
             b.next = False
         else:
             b.next = not a
     return hdl

def tb_ifnot():
     clock,reset = [Signal(bool(0)) for ii in range(2)]
     a = Signal(bool(0))
     b = [Signal(bool(0)) for ii in range(4)]

     tb_dut = [None for ii in range(4)]
     #b1,b2,b3,b4 = b  # no LoS ports
     tb_dut[0] = ifnot_1(clock,reset,a,b[0])
     tb_dut[1] = ifnot_2(clock,reset,a,b[1])
     tb_dut[2] = ifnot_3(clock,reset,a,b[2])
     tb_dut[3] = ifnot_4(clock,reset,a,b[3])

     @always(delay(2))
     def tb_clk():
         clock.next = not clock

     @instance
     def tb_stim():
         print('start')
         reset.next = False
         yield delay(10)
         for ii in range(4):
             assert b[ii] == False

         reset.next = True
         yield delay(10)
         for ii in range(4):
             assert b[ii] == (not a)
         print('end')

         raise StopSimulation

     return tb_clk, tb_stim, tb_dut

def convert_vhdl():
     clock,reset = [Signal(bool(0)) for ii in range(2)]
     a = Signal(bool(0))
     b = [Signal(bool(0)) for ii in range(4)]
     b1,b2,b3,b4 = b

     try:
         toVHDL(ifnot_1,clock,reset,a,b1)
         print('1 converted vhdl')
     except Exception, err:
         print('1 error vhdl %s' % (err))

     try:
         toVHDL(ifnot_2,clock,reset,a,b2)
         print('2 converted vhdl')
     except Exception, err:
         print('2 error vhdl %s' % (err))

     try:
         toVHDL(ifnot_3,clock,reset,a,b3)
         print('3 converted vhdl')
     except Exception, err:
         print('3 error vhdl %s' % (err))

     try:
         toVHDL(ifnot_4,clock,reset,a,b4)
         print('4 converted vhdl')
     except Exception, err:
         print('4 error vhdl %s' % (err))

def convert_verilog():
     clock,reset = [Signal(bool(0)) for ii in range(2)]
     a = Signal(bool(0))
     b = [Signal(bool(0)) for ii in range(4)]
     b1,b2,b3,b4 = b

     try:
         toVerilog(ifnot_1,clock,reset,a,b1)
         print('1 converted verilog')
     except Exception, err:
         print('1 error verilog %s' % (err))

     try:
         toVerilog(ifnot_2,clock,reset,a,b2)
         print('2 converted verilog')
     except Exception, err:
         print('2 error verilog %s' % (err))

     try:
         toVerilog(ifnot_3,clock,reset,a,b3)
         print('3 converted verilog')
     except Exception, err:
         print('3 error verilog %s' % (err))

     try:
         toVerilog(ifnot_4,clock,reset,a,b4)
         print('4 converted verilog')
     except Exception, err:
         print('4 error verilog %s' % (err))

if __name__ == '__main__':
     Simulation(tb_ifnot()).run()
     convert_vhdl()
     convert_verilog()
     toVHDL(tb_ifnot)
     subprocess.check_call('vcom pck_myhdl_08.vhd tb_ifnot.vhd', shell=True)
     subprocess.check_call('vsim -c -do -t 1ns run.do work.tb_ifnot', 
shell=True)
~~~~~~~~~~~~~~~~~