Re: [myhdl-list] VHDL Conversion Errors (was: Bug in generated code?)

[Norbo <Nor...@gm...>]

> On the #2 issues, since the MyHDL simulation != VHDL
> simulation, does this constitute an error, not sure?  I
> had a similar issue, I often used:
>
>         if reset:
>
> The myhdl simulation worked and Verilog conversion worked
> but the VHDL did not, the fix was to explicitly state:
>
>         if reset == False:
>
> Even though there was a simulation mismatch it was suggested
> that the "reset == False", is the desired form.  I am not sure
> if the mixed type comparison should be converted?  Instead, we
> probably want the converter to raise a conversion exception and
> not convert the code.

i am a bit confused:
when a negedge event on the reset is inserted in the sensitivity list,  
then it would
look like the following, right?

############## case 1 ###########

     if reset:

-->> conversion to vhdl works but would be the wrong value for the negedge  
event. right?



############## case 2 ###########

     if not reset:

-->> conversion to vhdl fails, with: Error:  No proper edge value test


############## case 3 ###########

     if reset== False:

-->> conversion to vhdl fails, with: Error:    No proper edge value test


############## case 4 ###########

     if reset== bool(0):

-->> conversion to vhdl fails, with: Error:    No proper edge value test


############## case 5 ###########

     if reset==0:

-->> The working version !!


greetings
Norbo