[myhdl-list] VHDL Conversion Errors (was: Bug in generated code?)

[Christopher F. <chr...@gm...>]

On 1/20/13 6:01 AM, Norbo wrote:
> This Code i think actually shows two glitches in the VHDL converter.
> One was already discussed here, but i think it has been forgotten. This is
> just to remember.
> Here the link: http://permalink.gmane.org/gmane.comp.python.myhdl/2218
>
>
<snip>
>

Let me try and summarize, we believe we have encountered
three different VHDL conversion errors.

    1. bitwise multiplication (there was the wider
    question if the types were correct but since the ops
    were invalid it was a moot point).

    2. An odd intbv(val) == bool(val) comparison error,
    python allows this check (what is the rule?) but when
    converted the mixed types is not a valid comparison?

    3. More than two operand math operations and resizing.

On the #2 issues, since the MyHDL simulation != VHDL
simulation, does this constitute an error, not sure?  I
had a similar issue, I often used:

        if reset:

The myhdl simulation worked and Verilog conversion worked
but the VHDL did not, the fix was to explicitly state:

        if reset == False:

Even though there was a simulation mismatch it was suggested
that the "reset == False", is the desired form.  I am not sure
if the mixed type comparison should be converted?  Instead, we
probably want the converter to raise a conversion exception and
not convert the code.

Now, the best way to keep track of these so we don't loose
track of them?

Regards,
Chris