Re: [myhdl-list] Bug in generated code?

[Norbo <Nor...@gm...>]

This Code i think actually shows two glitches in the VHDL converter.
One was already discussed here, but i think it has been forgotten. This is  
just to remember.
Here the link: http://permalink.gmane.org/gmane.comp.python.myhdl/2218


       from myhdl import *
       from random import randrange

       def TOP(outvalue,sel_value):

	  @always_comb
	  def combi_sel():
	    outvalue.next=1
	    if sel_value == bool(0):
	      outvalue.next=8
	    elif sel_value == bool(1):
	      outvalue.next[0]=sel_value[2]*sel_value[0] #8  
#sel_value[0]+sel_value[0]
	
	  return combi_sel
	
	
       def test_bench():
	  outsignal=Signal(intbv(0)[4:])
	  sel_value=Signal(intbv(0)[4:])
	  ###### add the unit too be tested#######
	  instanc_top=TOP(outsignal,sel_value)
	
	  @instance
	  def stimulus():
	    sel_value.next=0
	    yield delay(10)
	    for i in range(sel_value.max):
		sel_value.next=i
		yield delay(10)
		print "sel_value: ",sel_value,"\toutsignal:", outsignal
		
	    raise StopSimulation
	
	
	  return  stimulus,instanc_top

	
       if __name__ == '__main__':
	
	  ############ Simulation ################
	  sim = Simulation(test_bench())
	  print "#"*10+"Simulation Started" + "#"*10
	  sim.run()
	  print "#"*10+"Simulation Finished" + "#"*10
	
	
	
	  ############### Conversion ###############
	  print "Conversion To VHDL Started" + "-"*30
	  outsignal=Signal(intbv(0)[4:])
	  sel_value=Signal(intbv(0)[4:])
	  toVHDL(TOP,outsignal,sel_value)



Conclusion:
Simulation works !!,
VHDL conversion result with 0.8 dev version:


       -- File: TOP.vhd
       -- Generated by MyHDL 0.8dev
       -- Date: Sun Jan 20 12:50:43 2013


       library IEEE;
       use IEEE.std_logic_1164.all;
       use IEEE.numeric_std.all;
       use std.textio.all;

       use work.pck_myhdl_08.all;

       entity TOP is
	  port (
	      outvalue: out unsigned(3 downto 0);
	      sel_value: in unsigned(3 downto 0)
	  );
       end entity TOP;


       architecture MyHDL of TOP is


       begin




       TOP_COMBI_SEL: process (sel_value) is
       begin
	  outvalue <= "0001";
	  if (sel_value = False) then
	      outvalue <= "1000";
	  elsif (sel_value = True) then
	      outvalue(0) <= stdl(to_unsigned(sel_value(2), 1) *  
to_unsigned(sel_value(0), 1));
	  end if;
       end process TOP_COMBI_SEL;

       end architecture MyHDL;



Issues:
* There is no compare operator for unsigned(x downto 0) with the False.
In Line: "if (sel_value = False) then"
* There is no Function stdl(arg: unsigned) which takes the unsigned in the  
pck_myhdl_08.
In Line: "outvalue(0) <= stdl(to_unsigned(sel_value(2), 1) *  
to_unsigned(sel_value(0), 1));"




greetings

Norbo