Re: [myhdl-list] Bug in generated code?

[Thomas H. <th...@ct...>]

Christopher,

I changed your tb_stim instance slightly so that it produces
more output on mismatch.

     def tb_stim():
         print('start')
         for aa in range(a.min, a.max):
             for bb in range(b.min, b.max):
                 for cc in range (c.min, c.max):
                     for dd in range(d.min, d.max):
                         a.next = aa
                         b.next = bb
                         c.next = cc
                         d.next = dd
                         yield delay(4)
                         if x != (aa+bb - (cc+dd)):
                             print "Error in", aa, bb, cc, dd
                             print "Is", x, "Should be", (aa+bb - (cc+dd))
##                        assert x == (aa+bb - (cc+dd))
         print('end')
         raise StopSimulation

     return tb_dut, tb_stim

The myhdl simulation still runs without any errors or output,
simulating the VHDL code in xilinx isim starts with this output:

Simulator is doing circuit initialization process.
start
Finished circuit initialization process.
Error in 0 0 1 63
Is 0 Should be -64
Error in 0 0 2 62
Is 0 Should be -64
Error in 0 0 2 63
Is -1 Should be -65
ISim>
# run 1.00us
Error in 0 0 3 61
Is 0 Should be -64
Error in 0 0 3 62
Is -1 Should be -65
Error in 0 0 3 63
Is -2 Should be -66
Error in 0 0 4 60
Is 0 Should be -64
Error in 0 0 4 61
Is -1 Should be -65
Error in 0 0 4 62
Is -2 Should be -66
Error in 0 0 4 63
Is -3 Should be -67

So, MyHDL and VHDL disagree.  Changing the expression in math_abcd()
makes isim and myhdl agree:

def math_abcd(a,b,c,d,x):
     @always_comb
     def hdl():
         x.next = a + b - c - d
     return hdl

Thomas