Re: [myhdl-list] Bug in generated code?

[Christopher F. <chr...@gm...>]

On 1/18/13 2:43 PM, Thomas Heller wrote:
> Am 18.01.2013 21:11, schrieb Tom Dillon:
>> Thanks for the education. I would have to say I have been coding with
>> MyHDL like a "Verilog die-hard". I have been resizing myself never
>> thinking MyHDL might do that for me.
>>
>> One question, does MyHDL produce an error in simulation if (c + d) > 255?
>
> No, the MyHDL simulation worked perfectly; but the hardware (compiled
> from toVHDL and loaded into a FPGA) produced wrong results.  It took
> me some time to find the reason.
>
> Maybe I should have simulated the VHDL code also, but I did not.
>

I put an example that runs the MyHDL, VHDL, and Verilog
simulations here:

https://bitbucket.org/cfelton/examples/src/tip/math/example_math.py

As discussed, the VHDL simulation will fail and the MyHDL
and Verilog do not.  This is a simulation mismatch and it
is an issue that needs to be resolved.

Some thoughts on the correction.  One approach would to
resize all the operands to match the type of the LHS?

Regards,
Chris