Re: [myhdl-list] Bug in generated code?

[Christopher F. <chr...@gm...>]

On 1/18/2013 2:43 PM, Thomas Heller wrote:
> Am 18.01.2013 21:11, schrieb Tom Dillon:
>> Thanks for the education. I would have to say I have been coding with
>> MyHDL like a "Verilog die-hard". I have been resizing myself never
>> thinking MyHDL might do that for me.
>>
>> One question, does MyHDL produce an error in simulation if (c + d) > 255?
>
> No, the MyHDL simulation worked perfectly; but the hardware (compiled
> from toVHDL and loaded into a FPGA) produced wrong results.  It took
> me some time to find the reason.
>
> Maybe I should have simulated the VHDL code also, but I did not.
>
<snip>

I started attempting to compare the MyHDL simulation
vs. the VHDL simulation, I put the following together:

     from myhdl import *

     def math_abcd(a,b,c,d,x):
         @always_comb
         def hdl():
             x.next = a + b - (c + d)
         return hdl

     def example_math():
         Omax = 64
         Xmin,Xmax = (-1*(Omax*4), Omax*4)
         x = Signal(intbv(0, min=Xmin, max=Xmax))
         a = Signal(intbv(0, min=0, max=Omax))
         b = Signal(intbv(0, min=0, max=Omax))
         c = Signal(intbv(0, min=0, max=Omax))
         d = Signal(intbv(0, min=0, max=Omax))
         tb_dut = math_abcd(a,b,c,d,x)
         @instance
         def tb_stim():
             print('start')
             for aa in range(a.min, a.max):
                 for bb in range(b.min, b.max):
                     for cc in range (c.min, c.max):
                         for dd in range(d.min, d.max):
                             a.next = aa
                             b.next = bb
                             c.next = cc
                             d.next = dd
                             yield delay(4)
                             assert x == (a+b - (c+d))
             print('end')
             raise StopSimulation

         return tb_dut, tb_stim

     if __name__ == '__main__':
         Simulation(example_math()).run()
         toVHDL(example_math)
         toVerilog(example_math)


The MyHDL simulation works fine (as expected) for
all inputs (I reduced the bit widths so it would
run faster).  I did not get time to run the sims
yet.  The converter will create the above simple
test cases, should be able to run the VHDL and
Verilog directly.  Not sure when I will have time to
complete this ...

Regards,
Chris