Re: [myhdl-list] Bug in generated code?

[Thomas H. <th...@ct...>]

Am 18.01.2013 21:11, schrieb Tom Dillon:
> Thanks for the education. I would have to say I have been coding with
> MyHDL like a "Verilog die-hard". I have been resizing myself never
> thinking MyHDL might do that for me.
>
> One question, does MyHDL produce an error in simulation if (c + d) > 255?

No, the MyHDL simulation worked perfectly; but the hardware (compiled
from toVHDL and loaded into a FPGA) produced wrong results.  It took
me some time to find the reason.

Maybe I should have simulated the VHDL code also, but I did not.

Let me describe the approach that I took in my work (in case this is
interesting to on this mailing list):

The goal of my FPGA is to find the x/y coordinates of a small light
point on a 4-quadrant photodiode.  The equations for this are:

x = (a+b) - (c+d) / (a+b+c+d)
y = (a+d) - (b+c) / (a+b+c+d)

where a, b, c, d are the digitized currents through the four quadrants
of the photodetector, and x and y are the final coordinates.

First, my fpga read the digitized intensity values and transfers them
to the PC.  The PC calculates the x/y values with the above formulas and
displays the result x1/y1.

Then, I wrote a MyHDL module which (with some pipelining) also
calculates these values.  I constructed a simulation object, and fed
the a,b,c,d values read from the fpga to the instance, simulated a few
timesteps, retrived the values as x2/y2 from the MyHDL instance and
displayed this result also.  They were the same as x1/y1.

Finally, I converted the MyHDL instances to VHDL, compiled and loaded 
into the FPGA, together with code that transferred the values calculated
in the FPGA also to the PC, as x3/y3.

So, all the values x1/y1, x2/y2, x3/y3 should be the same:  The first
calculated by Python code, the second by the MyHDL simulation, the third
by the hardware.

Unfortunately, most of the time x3/y3 (calculated by the FPGA) were
wrong until I fixed the paranthesis in the MyHDL code.

Thomas