Re: [myhdl-list] Bug in generated code?

[Tom D. <TD...@Di...>]

Hi,

This is interesting but I don't think it would be a bug. I am not sure the
MyHDL specs call for automatic size conversions.


On Wed, Jan 16, 2013 at 1:26 PM, Thomas Heller <th...@ct...> wrote:

> I believe I have found a bug in the code generator.
>
> Here is the MyHDL code:
>
>      rx = Signal(intbv(0, min=-1024, max=1024)
>      a = Signal(intbv(0, min=0, max=256)
>      b = Signal(intbv(0, min=0, max=256)
>      c = Signal(intbv(0, min=0, max=256)
>      d = Signal(intbv(0, min=0, max=256)
>
>
>      rx.next = a + b - (c + d)
>
> and this is the generated VHDL code:
>
>      a: in unsigned(7 downto 0);
>      b: in unsigned(7 downto 0);
>      c: in unsigned(7 downto 0);
>      d: in unsigned(7 downto 0);
>
>      signal rx: signed (9 downto 0);
>
>      rx <= signed((resize(a, 10) + b) - (c + d));
>
> If I understand the VHDL code correctly, there is data
> lost in the (c + d) operation since the intermediate result has only
> 8 bits instead of the required 10 bits.
>

I am most used to Verilog, but if I were coding this in Verilog and didn't
wanted the c+d to grow, I would of forced them into an intermediate signal
that was one bit bigger and then performed the addition to guarantee the
carry was not lost.

I am not sure if this is any different in VHDL.

Also, I would not think that MyHDL would guarantee the growth either. There
are cases where you don't want it as well.

If I were coding this, I would also grow them before the addition if you
wanted the carry to count.

Others may have a better grasp of what MyHDL is supposed to do for this
case.

Yours,

Tom Dillon