[myhdl-list] Bug in generated code?

[Thomas H. <th...@ct...>]

I believe I have found a bug in the code generator.

Here is the MyHDL code:

     rx = Signal(intbv(0, min=-1024, max=1024)
     a = Signal(intbv(0, min=0, max=256)
     b = Signal(intbv(0, min=0, max=256)
     c = Signal(intbv(0, min=0, max=256)
     d = Signal(intbv(0, min=0, max=256)


     rx.next = a + b - (c + d)

and this is the generated VHDL code:

     a: in unsigned(7 downto 0);
     b: in unsigned(7 downto 0);
     c: in unsigned(7 downto 0);
     d: in unsigned(7 downto 0);

     signal rx: signed (9 downto 0);

     rx <= signed((resize(a, 10) + b) - (c + d));

If I understand the VHDL code correctly, there is data
lost in the (c + d) operation since the intermediate result has only
8 bits instead of the required 10 bits.

Restructuring the MyHDL code like this:
     rx.next = a + b - c - d
generates this VHDL code:
     rx <= signed(((resize(a, 10) + b) - c) - d);
which looks correct to me.

Note that I'm using MyHDL 0.7, have not tried the newer version.

Thomas