Re: [myhdl-list] Next Python to VHDL generator by using LLVM

[Christopher F. <chr...@gm...>]

On 1/15/2013 11:45 AM, David Blubaugh wrote:
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> To All,
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> I was wondering if someone has looked in the use of the LLVM to be able to generate full featured python into synthesizable VHDL with simulation support of course ??
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> I STRONGLY BELIEVE YOU GUYS NEED TO LOOK AT LLVM for greatly enhancing MyHDL to support a greater domain of the python language to support synthesizable designs and testbench support.
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> David Blubaugh
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I completely disagree this is *not* something the MyHDL
group should be interested in.  There would be no benefit
for the MyHDL folks to look at this.

In addition, other than a buzz word you didn't provide
any technical arguments why this would be desirable.

Regards,
Chris